1. Field of the Invention
Non-volatile semiconductor memory systems having multiple power states are described. More specifically, components and methods for improving utilization and reducing power requirements of flash memory systems that include sub- or near-threshold components are described.
2. Description of the Related Art
In general, in the descriptions that follow, the first occurrence of each special term of art that should be familiar to those skilled in the art of integrated circuits (“ICs”) and systems will be italicized. In addition, when a term that may be new or that may be used in a context that may be new, that term will be set forth in bold and at least one appropriate definition for that term will be provided. In addition, throughout this description, the terms assert and negate may be used when referring to the rendering of a signal, signal flag, status bit, or similar apparatus into its logically true or logically false state, respectively, and the term toggle to indicate the logical inversion of a signal from one logical state to the other. Alternatively, the mutually exclusive boolean states may be referred to as logic_0 and logic_1. Of course, as is well known, consistent system operation can be obtained by reversing the logic sense of all such signals, such that signals described herein as logically true become logically false and vice versa. Furthermore, it is of no relevance in such systems which specific voltage levels are selected to represent each of the logic states.
Hereinafter, reference to a facility shall mean a circuit or an associated set of circuits adapted to perform a particular function regardless of the physical layout of an embodiment thereof. Thus, the electronic elements comprising a given facility may be instantiated in the form of a hard macro adapted to be placed as a physically contiguous module, or in the form of a soft macro the elements of which may be distributed in any appropriate way that meets speed path requirements. In general, electronic systems comprise many different types of facilities, each adapted to perform specific functions in accordance with the intended capabilities of each system. Depending on the intended system application, the several facilities comprising the hardware platform may be integrated onto a single IC, or distributed across multiple ICs. Depending on cost and other known considerations, the electronic components, including the facility-instantiating IC(s), may be embodied in one or more single- or multi-chip packages. However, unless expressly stated to the contrary, the form of instantiation of any facility shall be considered as being purely a matter of design choice.
Non-volatile solid-state memory systems are widely used in a variety of mobile and handheld devices, notably smart phones, tablets, laptops, and other consumer electronics products. Solid state memory, which can include embedded or stand-alone charge-based flash memory, phase change memory, resistive RAM (“RRAM”), or magneto-resistive memory (“MRAM”), is of particular advantage for battery operated mobile devices that have limited available power. Typically, electronic systems in such devices have processors, microcontrollers (“MCUs”), or other electronic controllers that support architected power states (e.g., an active state, a stand-by or sleep state, a deep sleep state, etc.). As compared to active states, the power consumption in these electronic systems can be significantly reduced when the device is maintained in stand-by or sleep states.
Shown in FIG. 1 is a typical general purpose computer system 10. Although not all of the electronic components illustrated in FIG. 1 may be operable in the sub-threshold or near-threshold domains in any particular embodiment, some, at least, may be advantageously adapted to do so, with concommitant reductions in system power dissipation. In particular, in recently-developed battery-powered mobile systems, such as smart-phones and the like, many of the discrete components typical of desktop or laptop devices illustrated in FIG. 1 are integrated into a single integrated circuit (“IC”) chip. The Parent Provisional and Related Applications discloses several circuits adapted to operate in the sub-threshold domain.
Shown in FIG. 2 is a typical integrated system 12 comprising, inter alia, reference voltage (“VRef”) generator 14, reference current (“IRef”) generator 16, several digital modules, and several analog modules. An example of an analog module is analog to digital converter (“ADC”) 18. Reference voltage generator 14 and reference current generator 16 are each common modules for supplying a stable reference to such analog modules. Reference voltage generator 14 is sometimes used to derive the output reference current provided by reference current generator 16. Also, reference voltage generator 14 and reference current generator 6 may be used to supply a stable reference to modules throughout integrated system 12.
For convenience of reference, in the system illustrated in FIG. 2, one instantiation of the voltage converter 20 is illustrated. In general, the voltage converter 20 is adapted to deliver to a load, e.g., any of the several components comprising system 12, a regulated voltage having a selected one of a first current capability and a second current capability substantially less than the first current capability. In one embodiment of voltage converter 20, at least one of the first and second voltages is dynamically adjusted as a function complementary to absolute temperature.
Shown in greater detail in FIG. 3 is one embodiment of the adaptive voltage converter 20. A battery 22 supplies a voltage, VBat, to converter 20, which generates a lower regulated voltage, VReg, that may be delivered to a load circuit 24, which can be a circuit of any type. The voltage VReg may be sub-threshold, near-threshold or super-threshold. In general, the converter 20 may comprise two or more voltage converters/regulators 26, of which only two are illustrated in FIG. 3. A multiplexing circuit 28 selects between the outputs of the several converters/regulators 26 depending on the state of a control signal 30 generated by a control facility 32. Control 32 also selectively enables and/or disables each of the converters/regulators 26; and a voltage reference VRef generator 34. In addition to basic voltage regulation, the converter 20 may be adapted to change the output of each converter/regulator 26 based on a number of variables, including, for example, process corner, temperature and input voltage. Details of important elements and variants of the adaptive voltage converter 20, as well as a specific implementation, are disclosed in Related Application 1.
As disclosed in Related Application 1, the embodiment illustrated in FIG. 3, converter 20 comprises two converters: a buck converter 26a for high-efficiency conversion during active mode, and a linear voltage regulator 26b for ultra-low quiescent current operation during sleep mode. If one of the converters 26 is in use, it would be typical to power down the other unused converter 26 to save energy. In this embodiment, the buck converter 26a will generally be enabled when the system 12 is in active mode with loads on the order of 100 μA to 5 mA. In such a mode, buck converter 26a is capable of delivering power at a variety of voltages (including sub-threshold and near-threshold voltages) with power efficiencies exceeding 90%. However, load currents in a sub-threshold or near-threshold circuit may fall below 100 nA in a sleep mode, and the power efficiency of buck converter 26a could easily fall below 5%. In this sleep mode, it may be desirable to switch over to a second converter that offers better power efficiency. For example, linear voltage regulator 26b can be easily adapted to operate with quiescent current on the order of 1 nA yet be capable of delivering much great power efficiency with load currents on the order of 100 nA. Typically, such an embodiment of linear voltage regulator 26b will be incapable of sourcing active load currents in the range of 100 μA to 5 mA, but automatic switchover to the buck converter 26a in active mode solves this problem.
Optimizing the power consumption of an MCU-based system requires some mechanism to measure energy usage over time and during various types of operations, which allows system designers to develop software adapted dynamically to reduce power. Many MCUs include a number of standard counters, e.g., in the Peripherals facility (see, FIG. 2), which may be used in a variety of ways to enable power measurement without adding hardware cost.
Traditional low power systems-on-a-chip (“SOC”) implementations typically include an integrated power supply unit (“PSU”) to supply power to the MCU chip and to the system as a whole. Linear voltage regulators are provided in the PSU for low current consumption modes where they are extremely efficient. The PSU typically contains one or more buck converters to provide the higher currents necessary when the system is in normal operation with main loads turned on. Buck converters are typically more efficient than linear voltage regulators in these high current load cases. In general, buck converters operate by injecting current from a high-voltage source rail into a lower-voltage drive rail which supplies the system with its operating current. In either form of power supply, linear regulator or buck converter, it is difficult (if not impossible) to directly quantize the delivered output current using circuits amenable to integration into a single IC. Accordingly, indirect monitoring approaches are usually employed. For example, one possible approach would be to develop, either empirically or using a simulation facility, an estimate of the power consumption of a particular SOC facility each time it is engaged, then counting the number of times so engaged within a selected monitoring period; total consumed power can thus be estimated by simply multiplying the heuristic power estimate per engagement by the number of engagements. By way of example, the facility of interest might be an arithmetic and logic unit (“ALU”) within the CPU which is adapted to execute each of a plurality of pre-defined program instructions as integral units of work. Prior art power management units (“PMUs”) of this type have been proposed to facilitate chip- or module-level thermal management. However, such approaches are relatively gross and provide, at best, very coarse-grained energy consumption measurements, which are of little utility in managing power consumption is near real-time.
What is needed is a method and apparatus adapted to quantize energy being delivered by the PSU in relatively small, integral units. Monitoring this fine-grained quantized data stream over time will better facilitate energy management in near real-time.